In particular I wanted to compare the differences between the Cortex M families (since my familiarity and comfort resides there).
So below is a little bit of what I've learned:
(a lot of this is from Wikipedia's article on ARM: http://en.wikipedia.org/wiki/ARM_Cortex-M
The ARM
Architecture: With every ARM® core comes a level of standardization that
eliminates future architectural upgrades or software tool changes.
Cortex M- Processor with
Coding in Mind: Focused particularly
on the instruction set and optimizing functions to deliver higher performance,
offering more peripherals and ease development time. ARM® Cortex-M Series is the Microcontroller line of Thumb2
instruction set, making it the only of the ARM® cores allow programming
exclusively in C/C++. With integrated
hardware to optimize the code development process—the Cortex M- is focused on
getting developers to a faster time to market.
The M-Cores: Offering a full 32-bit processor , the first
core to be released was the Cortex M3, offering a clear migration path for
ARM7TDMI processors. The M0 was released after as a subset features to the M3,
focused on low cost and less instruction sets.
Cortex M4 offers expanded instruction sets and the addition of the
Cortex M4F also adds DSP functionality with floating point capability.
Comparing the ARMv7 and the Cortex M- ARM Processors TI Tech Day- St. Paul MN 2010
This includes ALL of the M-
families from M0 to M4
The M family is also unique in
that it is the ONLY family in the A-R-M that can be programmed entirely with C
code. It does not require assembly code, but if you want to write in it... you can, but it's not needed.
All of the instruction sets are
backward compatible.
This means instructions written
on M0 will work on a M1, what is on a M1 will work on the M3 and what is on the
M3 will work for the M4.
Looking at the Instruction Sets:
| ARM Cortex-M |
Thumb | Thumb-2 | Hardware Multiply |
Hardware Divide |
Saturated Math |
DSP Extensions |
Floating Point |
ARM Architecture |
|---|---|---|---|---|---|---|---|---|
| No | No | No | No | |||||
| No | No | No | No | |||||
| Entire | Entire | 1 cycle | Yes | Yes | No | No | ||
| Entire | Entire | 1 cycle | Yes | Yes | Yes |
Note: The Cortex-M0 and M1 only include these Thumb-2 instructions: BL, DMB, DSB, ISB, MRS, MSR.[5][6]
(From Wikepedia: http://en.wikipedia.org/wiki/ARM_Cortex-M)
Initially I thought the ARM M0 was the very first M- processor, but it appears that instead it's a cost optimized one with stripped down instruction sets.
It was the M3 that was originally released and licensed. **I don't want to mislead anyone in the progression of Instruction sets below:
A few reasons why a semiconductor firm would want to license this core is to 1.) add the M- class 32 bit functionality, cheaper license from ARM, less instruction sets and theoretically less power consumption (although Power Consumption is something that has more to do with the core's interfaces to the peripherals). There is a version of the M0 that is the M0+ that a lot of providers licensed that offers a few more instruction sets than just the M0. Although, looking at cost of these chips--- they aren't really THAT much cheaper than the M3's.
A few reasons why a semiconductor firm would want to license this core is to 1.) add the M- class 32 bit functionality, cheaper license from ARM, less instruction sets and theoretically less power consumption (although Power Consumption is something that has more to do with the core's interfaces to the peripherals). There is a version of the M0 that is the M0+ that a lot of providers licensed that offers a few more instruction sets than just the M0. Although, looking at cost of these chips--- they aren't really THAT much cheaper than the M3's.
Expansion to the M1 Core.
This has much more instruction sets, which overall helps reduce the code required. It really looks like the only people who license this core are the FPGA vendors for their "soft" and "flexible" cores. I suspect that this core has a lot of chip communications features as well as still maintains the "hosuekeeping" functions that M0 has.
This has much more instruction sets, which overall helps reduce the code required. It really looks like the only people who license this core are the FPGA vendors for their "soft" and "flexible" cores. I suspect that this core has a lot of chip communications features as well as still maintains the "hosuekeeping" functions that M0 has.
This is the M3, the original M- core that was out to liscense. This is also the one that I see the most comparison against. Basically it's a microcontroller that has supercharged abilities. Each silicon manufactorer has choices in the architecture to either optimize for cost or preformance. With these specialized instruction sets-- the overall chip can be sectioned to be tweaked towards specific functions (e.g. Motion Control, or Human Interfacing). However, the M3 still functions primarily as a Microcontroller, which brings me to this guy... the M4
The M4 and the M4F is what starts to take the M- core past it's Microcontroller roots into a grey area with DSP functionality. Just like the TI TMS32C2000 chips are considered Microcontrollers, but ultimately have enough DSP functions to be a DSP--- the M4 and the M4F joins the ranks as a Microcontroller that spans the Microcontroller/DSP delineation. The Floating point capability is an additional license cost to the manufacturer.
*Reminder for me to do some research to find out if there is some sort of volume discount-- to find out why particular semi-conductor companies only choose to license certain cores, or if you license a larger core you get all of the smaller ones too...
*Also I need to look into what is entailed in using a core. How much on a chip is a manufacturer's and how much is dictated by ARM. This will help me understand exactly how much is cross compatible.
 |
| Source: Swanland 2012 using Avnet Express's carting option + wikipedia |
NXP has a really good ARM marketing portal that is filled with information, I recommend looking at the NXP's ARM Cortex M- Products Brochure.
ARM has a nice white paper on the Cortex M3 I read a while ago. Cortex M3- Introduction.
